Trashernet

-- 10BASE-T Ethernet entirely in an FPGA — no external PHY needed!

Not necessarily compliant to any specification, but functional! This project includes the hardware, FPGA, and software design of a board designed to run Zephyr web socket applications on the SERV minimal RISC-V processor with plenty of working memory and storage.

TODO

This article is still a work in progress.

Resources

• Trashernet SoC Git repository [1]
• Trashernet (FPGA Ethernet core) Git repository [2]
• Zephyr OS [3]

Gallery

Sources:
    [1]: https://git.notsyncing.net/electronics/trashernet-soc
    [2]: https://git.notsyncing.net/fpga/trashernet
    [3]: https://zephyrproject.org/

Tags: fpga hardware